The invention relates generally to improved methods and apparatus for exercising and testing memory devices, and, more particularly, to burn-in and tests of integrated circuit memories.
It is well recognized that failures in integrated circuit and electronic devices tend to occur in the first part of the life cycle. Furthermore, the repair or replacement of integrated circuits in assembled systems in the field is expensive both from the point of view of performance of the repair and from the significant system down-time which may result as well as from errors which may have been introduced in the system because of the failed part. To reduce the number of failures in newly installed systems, it is not uncommon to exercise the device at an elevated temperature or, in what is known as a burn-in operation, before the device is assembled into a system, in addition to performing standard operational tests on the device.
The purpose of the burn-in operation is not only to test the operability of the device, but to exercise and stress the circuitry in order to allow the circuitry to mature and to cause the failure of any circuits which are only marginally operable and which will fail in the early part of the life cycle. Prior art testing arrangements typically apply randomly generated data words to a memory for burn-in and test purposes with the assumption that the majority of all possible combinations, which could cause failures, will be generated. It is recognized that a greater stress is applied to the memory devices when the memory devices are written sequentially by a selected data bit and its complement in order to switch the circuits more often. One prior art patent, U.S. Pat. No. 5,138,619 describes the application of randomly generated test pattern to a number of address locations of a memory device followed by applying the complemented test pattern in order to provide maximum stress on the memory device. A problem, however, with this prior art arrangement and all other prior art arrangements that apply randomly generated test patterns is that there is no assurance that a specific pattern, such as consecutive 0's and 1's for all combinations of bits, will be generated. In order to increase the probability that all desired patterns will be generated, the test cycle may be increased. However, not all bits may be switched with the same frequency for the purpose of stimulating failures in weak devices.
In large scale integrated circuitry, it is not uncommon to use built-in self tests (BIST) circuits for operational and burn-in testing which often include pseudo-random pattern generators as well as complex state machine logic circuitry and the necessary analysis circuitry to determine pass or failure of the test. A problem with BIST systems is the costs of the additional circuitry in terms of silicon real estate and the attendant concern for failures in the test circuitry itself. It is an object of the invention to provide a test arrangement generating optimum burn-in or test patterns which can be repeatedly applied and at high speed and which will perform specific tests such as testing for the influence of adjacent bits when written concurrently. It is a further object of the invention to be able to provide a test system in which a selected test pattern can be repeatedly applied and be complemented with minimal hardware addition to the integrated circuitry.